1. Field of the Invention
The invention relates to a device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal, wherein the stream of databits of the source signal is divided into n-bit source words, which device comprises converting means conceived to convert said n-bit source words into corresponding m-bit channel words in accordance with a conversion of the parity preserve type, where m and n are integers, with m&gt;n.
The invention also relates to a method of encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal, wherein the stream of databits of the source signal is divided into n-bit source words, said source words being converted into corresponding m-bit channel words in accordance with a conversion of the parity preserve type, where m and n are integers, with m&gt;n.
The invention further relates to a binary channel signal comprising a stream of databits, converted from a binary source signal comprising a stream of databits, wherein the stream of databits of the source signal comprises n-bit source words, the channel signal comprising m-bit channel words, each one of said m-bit channel words corresponding to one of said n-bit source words in accordance with a conversion of the parity preserve type, where m and n are integers, with m&gt;n.
The invention further relates to a record carrier comprising a binary channel signal comprising a stream of databits, converted from a binary source signal comprising a stream of databits, wherein the stream of databits of the source signal comprises n-bit source words, the channel signal comprising m-bit channel words, each one of said m-bit channel words corresponding to one of said n-bit source words in accordance with a conversion of the parity preserve type, where m and n are integers, with m&gt;n.
The invention further relates to a device for decoding a stream of databits of a binary channel signal into a stream of databits of a binary source signal, wherein the stream of databits of the channel signal is divided into m-bit channel words, which device comprises deconverting means conceived to deconvert said m-bit channel words into corresponding n-bit source words in accordance with a deconversion of the parity preserve type, where m and n are integers, with m&gt;n.
2. Description of the Relate Art
An encoding device and a decoding device mentioned in the foregoing are known from U.S. Pat. No. 5,477,222 (PHN 14448). The document discloses a device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal, satisfying a (1,7) runlength constraint. This means that, in a serial datastream of the channel signal, minimally one `zero` and maximally seven `zeroes` are present between two consecutive `ones` in the channel signal. The device further realizes a minimization of the repeated minimum transition runlength.
In this respect it should be noted that, normally, an additional precoding step, such as a 1T precoding, is applied to the (1,7) constrained sequence, resulting in a runlength-limited sequence with a minimum runlength of 2 and a maximum runlength of 8.
The known conversion is parity preserving (PP). `Parity preserving` means that the parity of the n-bit source words to be converted equals the parity, after modulo-2-addition, of the corresponding m-bit channel words in which they are converted. As a result, the encoding device as claimed does not influence the polarity of the signal.
As the conversion is parity preserving, DC-control can be applied by inserting DC-control bits in the datastream of the source words, which is more efficient than the insertion of extra bits in the channel bitstream, the so-called merging bits. DC-control implies the reduction of the power of the channel bit stream near zero frequency. The spectral notch at DC allows retrieval of the threshold level from the detected waveform, which is essential for detection and timing-recovery with the PLL.
In this PP channel code, no additional DC-control is present in order to further reduce the power of the channel bit stream near zero frequency, or to reduce the overhead for DC-control by reduction of the number of parity preserve DC-control bits.